The preferred embodiments relate to a computation system including a digital entropy signal generation apparatus and method.
In digital or other computational systems, entropy is randomness that may be generated by hardware or software and is typically output in a sequence of random numbers or symbols. Such entropy has various uses, such as in statistical sampling, computer simulation, and securing data from interception or theft, including by cryptography, by ways of example. Cryptography typically includes one or more keys that must be randomly generated, where the keys are used to encrypt data when transmitted and decrypt the encrypted data when received, and the greater the randomness associated with the key(s) the more difficult unauthorized third party decryption (i.e., without the authorized key) becomes. As other cryptography examples, randomness may use used for other inputs, such as for generating digital signatures or challenges in authentication protocols. In all events, in such uses, typically the more true randomness provided by the entropy-creating system, the better the performance of the application relying on that system. Measures of randomness typically determine whether a pattern exists or is discernable in the output sequence of the random generating system. Indeed, the National Institute of Standards and Technology (NIST) includes various publications, tools, and guidance toward developing statistical measures and implementations for detecting and improving the level of randomness in binary sequences.
While the prior art includes various manners of creating random numbers, additional considerations of complexity arise in that many applications now and in the future benefit from having random number generation onboard of a system level processor, such as a microprocessor, digital signal processor (DSP), microcontroller unit (MCU), or other comparable integrated circuit device. For example, design of such devices typically includes considerations of cost in terms of area and power consumed on or by the device, where such considerations may impede or prohibit the use of an integrated random number generator. Moreover, processor clock speed may be incompatible with the clock speeds necessary to generate random numbers according to prior art approaches.
Given the preceding discussion, while the prior art approaches may be acceptable in certain implementations, some applications may have requirements that are not sufficiently addressed by the prior art. Thus, the present inventors seek to improve upon the prior art, as further detailed below.